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HC05V7GRS/D 数据表(PDF) 126 Page - NXP Semiconductors

部件名 HC05V7GRS/D
功能描述  Low cost, HC05 Core
PDF  170 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC05V7GRS/D 数据表(HTML) 126 Page - NXP Semiconductors

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SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 112
MC68HC05V7 Specification Rev. 1.0
15.5
MDLC MUX INTERFACE
The MUX Interface is responsible for bit encoding/decoding and digital noise filtering
between the Protocol Handler and the Physical Interface.
15.5.1
Rx DIGITAL FILTER
The Receiver section of the MDLC includes a digital low pass filter to remove narrow noise
pulses from the incoming message. An outline of the digital filter is shown below.
Physical Interface
To CPU
Protocol Handler
MUX Interface
CPU Interface
Rx/Tx
Buffers
To J1850 Bus
MDLC
Figure 15-9:
MDLC Rx Digital Filter Block
4-Bit Up/Down Counter
Data
Latch
up/down
= 15
s
q
Filtered
Rx Data Out
MUX Interface Clock
Input
Sync
dq
Rx Data
from
Physical
Interface
(RxP)
= 0
r
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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