P89LPC930FDH datasheet(30/55 Pages) NXP

30 / 55 page

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 — 15 December 2004

30 of 55

9397 750 14472

8.18 I2C-bus serial interface

I2C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves.

• Multimaster bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer.

• The I2C-bus may be used for test and diagnostic purposes.

A typical I2C-bus conﬁguration is shown in Figure 7. The P89LPC930/931 device

provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.

Fig 7.

I2C-bus conﬁguration.

OTHER DEVICE

WITH I2C-BUS

INTERFACE

SDA

SCL

OTHER DEVICE

WITH I2C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

P89LPC930/931

I2C-BUS

002aaa433

P89LPC930FDH 数据表(PDF) 30 Page - NXP Semiconductors

P89LPC930FDH 数据表(HTML) 30 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表下载