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P89LPC930FDH 数据表(PDF) 44 Page - NXP Semiconductors |
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P89LPC930FDH 数据表(HTML) 44 Page - NXP Semiconductors |
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44 / 55 page  Philips Semiconductors P89LPC930/931 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 05 — 15 December 2004 44 of 55 9397 750 14472 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 11. Dynamic characteristics Table 8: AC characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °Cto+85 °C for industrial, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fosc =12MHz Unit Min Max Min Max fRCOSC internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz fWDOSC internal watchdog oscillator frequency 320 520 320 520 kHz fosc oscillator frequency 0 12 - - MHz tCLCL clock cycle see Figure 20 83 - --ns fCLKP CLKLP active frequency 0 8 - - MHz Glitch filter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock tCHCX HIGH time see Figure 20 33 tCLCL − tCLCX 33 - ns tCLCX LOW time see Figure 20 33 tCLCL − tCHCX 33 - ns tCLCH rise time see Figure 20 -8 - 8 ns tCHCL fall time see Figure 20 -8 - 8 ns Shift register (UART mode 0) tXLXL serial port clock cycle time 16 tCLCL - 1333 - ns tQVXH output data set-up to clock rising edge 13 tCLCL - 1083 - ns tXHQX output data hold after clock rising edge -tCLCL + 20 - 103 ns tXHDX input data hold after clock rising edge -0 - 0 ns tDVXH input data valid to clock rising edge 150 - 150 - ns SPI interface fSPI Operating frequency 2.0 MHz (Slave) 0 CCLK ⁄6 0 2.0 MHz 3.0 MHz (Master) - CCLK ⁄4 - - MHz tSPICYC Cycle time see Figures 15, 16, 17, 18 2.0 MHz (Slave) 6 ⁄ CCLK - 500 - ns 3.0 MHz (Master) 4 ⁄ CCLK - --ns tSPILEAD Enable lead time (Slave) see Figures 17, 18 2.0 MHz 250 - 250 - ns |
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