STPM066S datasheet(47/67 Pages) STMICROELECTRONICS

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Table 16. WD_REC_en OTP

Bit Nb

Name

Description

Row 8

Bit6

OTP_WD_REC_en

When OTP bit = 0, SPI bit = 0 make a WD failure to assert RESET_B but not affect the FSM.

All regulators keep running in active mode. If the SPI bit = 1 WD failure asserts RESET_B and

makes FSM go to REC state.

When OTP bit = 1, a WD failure asserts RESET_B and makes FSM go to REC state.

Table 17. OvRst_EN

Bit num

Name

Description

Row 8

Bit5

OvRst_EN<0>

OV assert RESET_B enable for BUCK and LDO

0: no OV of regulator can assert RESET_B;

1: the OV of regulator that is in the reset activation list can assert RESET_B.

Table 18. Prg Flag OTP

Bit Nb

Name

Description

Row 9

Bit15:13

OTP_Prg_Flag

When OTP bit = "000", the fsm goes to OTP programming mode

When OTP bit != "000", the Buck is enabled

Table 19. Buck CFG

Bit num

Name

Description

Row 9

Bit9

freqsel<0>

Free Running Frequency selection

0: 0.4 MHz programming

1: 2.4 MHz

Row 9

Bit8

cursel<0>

Max current selection

0: 1.5 A

1: 3.0 A programming

Row 9

Bit7:5

vsel<2:0>

Output Voltage selection

000: 5.0 V

001: 3.6 V

010: 3.3 V

011: 1.5 V

100: 1.35 V

101: 1.2 V

110: 1.1 V

111: 1.0 V

Table 20. Enables

EnLDO

EnBoost

EnVREF

enable of LDO

0: disable

1: enable

enable of Boost

0: disable

1: enable

enable of VREF

0: disable

1: enable

STPM066S

OTP bit mapping and register configuration

DS12976 - Rev 2

page 47/67

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