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VIPERGAN50 数据表(PDF) 13 Page - STMicroelectronics

部件名 VIPERGAN50
功能描述  Advanced quasi-resonant offline high voltage converter with E-mode GaN HEMT
PDF  37 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

VIPERGAN50 数据表(HTML) 13 Page - STMicroelectronics

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When the power is applied to the circuit, the gate of the high-side GaN (HS GaN) is pulled up through the resistor
RHV and capacitor CHV. If the voltage is high enough, the internal current generator draws the current ICHARGE
(3.55 mA typ.) to charge the capacitor connected between VDD and GND. To avoid excessive IC dissipation
in case VDD is accidentally shorted to GND, this current is initially reduced to 0.6 mA, until VDD is lower than
VDD_FOLD.
Figure 11. High voltage start-up generator: internal schematic and pin configuration
Driver
G
S
D
LS
GaN
Sense-EN
Lin Reg
DRAIN
HV
DRV
HVclamp
VDD
SW1
SW2
IOVP
BR
RHV
RiOVP
RBR
SW3
VBUS
Transformer’s
Primary
Inductance
SGND
Cvcc
Cdrv
ICHarge
UVLO
Logic
CHV
CBR
GND
Once VDD reaches the VDD-ONREG threshold, the linear regulator that feeds the DRV pin is turned on and DRV
voltage is charged.
Once VDD reaches the start-up threshold VDD-ON:
1.
The control logic disables the internal current generator;
2.
The switch SW1 is open and the HV pin is clamped to 27 V through HVclamp;
3.
The switch SW2 is closed to pull the GaN gate to zero;
4.
The switch SW3 is closed, internally connecting the pins HV and iOVP;
5.
Finally, the LS MOSFET is turned on and its drain-to-source resistance RDS(ON)LS is used as sense resistor.
The switching activity can commence only if VDRV is higher than the VDRV-OK threshold.
The DRV pin voltage is not upper limited, but the driver does not transfer gate signal if VDRV is accidentally set to
a voltage higher than 7 V typ.
The DRV linear regulator could experience voltage drops due to insufficient VDD or excess of loading. To avoid
incorrect GaN driving, the switching activity is interrupted if VDRV drops below (VDRV-OK – Hysteresis).
In case of VDD reduction below VDD-off, the switching activity is immediately interrupted and the GaN is converted
to operate as high voltage startup.
The UVLO threshold is used to completely reset the internal logic when crossed downwards.
VIPERGAN50
High voltage start-up generator and supply structures
DS13888 - Rev 2
page 13/37



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