STM32G0C1NET6X datasheet(121/159 Pages) STMICROELECTRONICS

121 / 159 page

DS13564 Rev 4

121/159

STM32G0C1xC/xE

Electrical characteristics

124

Figure 34. I2S slave timing diagram (Philips protocol)

1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

4.5

th(SD_SR)

Slave receiver

tv(SD_ST)

Data output valid time -

slave transmitter

after enable edge; 2.7 < VDD < 3.6V

after enable edge; 1.65 < VDD < 3.6V

tv(SD_MT)

Data output valid time -

master transmitter

after enable edge

5.5

th(SD_ST)

Data output hold time -

slave transmitter

after enable edge

th(SD_MT)

Data output hold time -

master transmitter

after enable edge

1. Based on characterization results, not tested in production.

Table 76. I2S characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Max

Unit

MSv39721V1

CPOL = 0

CPOL = 1

tc(CK)

WS input

SDtransmit

SDreceive

tw(CKH)

tw(CKL)

tsu(WS)

tv(SD_ST)

th(SD_ST)

th(WS)

tsu(SD_SR)

th(SD_SR)

MSB receive

Bitn receive

LSB receive

MSB transmit

Bitn transmit

LSB receive(2)

LSB transmit(2)

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