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STM32G0C1NET6X 数据表(PDF) 18 Page - STMicroelectronics |
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STM32G0C1NET6X 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 159 page ![]() Functional overview STM32G0C1xC/xE 18/159 DS13564 Rev 4 Figure 2. Power supply overview 3.7.2 Power supply supervisor The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of four thresholds for rising VDD and other four for falling VDD. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to VPVD threshold. It allows generating an interrupt when VDD level crosses the VPVD threshold, selectively while falling, while rising, or while falling and rising. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.3 Voltage regulator Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero. However, SRAM data retention is possible in Standby mode, in which case the LPR remains active and it only supplies the SRAM. MSv63104V2 VDDA domain RTC domain D/A converter A/D converter Standby circuitry (Wakeup, IWDG) Voltage regulator Core SRAM Digital peripherals Low-voltage detector LSE crystal 32.768 kHz osc BKP registers RCC BDCR register RTC and TAMP Comparators Voltage reference buffer I/O ring VCORE domain Temp. sensor Reset block PLL, HSI Flash memory VDDIO1 VREF+ VDD domain VCORE VSS/VSSA VDD/VDDA VBAT VDDA VREF+ VSSA VSS VDD VDDIO1 domain I/O ring USB VDDIO2 domain VDDIO2 VDDIO2 |
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