So the maximum output voltage in worst case condition at ambient temperature is 3.768 V + 0.75 mVRMS instead

of 3.75 V expected. This represents an error on the current reading of about 2.1%. 1% more must be added due

to the shunt accuracy.

It is important to note that this calculus has been done by using all the maximum values and all the error terms

have been added to each other, meaning that the chance of getting 2.1% precision in the above use case is

extremely low and on the whole population, the error is considerably smaller.

6.7

Stability

•

Driving switched capacitive loads

Some ADC get their signal thanks to a sample and hold capacitor. If before a sampling this capacitance is fully

discharged, a fast current load can appear on the output of the TSC21x during the sampling phase.

The scope probe below in Figure 36 shows the output voltage of the TSC213 excited through a 40 pF capacitor

with a 3.3 Vpp signal at 5 kHz to simulate the sample and hold circuit of an ADC.

Figure 36. Capacitive load response at Vcc = 3.3 V

-40µ

-20µ

0

20µ

40µ

60µ

80µ

100µ

120µ

140µ

-8

-7

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

-800

-700

-600

-500

-400

-300

-200

-100

0

100

200

300

400

500

600

700

800

Time (s)

Sample and hold

Vout

Vcc = 3.3 V, Vicm = 1.65V, Vsense = 0Vpp

T = 25°C,

5 kHz square signal of 3.3 V amplitude

injected in the output through 47pF

The graph in Figure 36 shows the behavior of the output of the TSC213 under worst case condition, as for

example, when there is an ADC channel change between two measurements.

If a single channel is used, the change on the sample and hold capacitance is certainly very small, and so the

recovery time is extremely low as described by Figure 37.

TSC210, TSC211, TSC212, TSC213, TSC214, TSC215

Stability

DS13237 - Rev 6

page 19/38