6.8

Improving precision

If the TSC21x series current sensing is used with an ADC, it can be interesting to sense the output and the

reference voltage applied on the Ref pin in a differential way as depicted in Figure 43.

There are least two benefits to realizing the measurement in this way.

Firstly, in case of the output common voltage being fixed thanks to the ref pin, done only with a resistor divider,

without any buffer, it can cancel the effect of this external impedance.

And secondly, it cancels the imprecision of the voltage reference source as well, as it serves as reference also for

the ADC.

Figure 43. ADC in differential mode

TSC21x

Vcc

+

-

Vref

Ct

100nF

ADC

Rs

6.9

Power supply recommendation

In order to decouple correctly the TSC21x, it is recommended to place a 100 nF bypass capacitor between Vcc

and Gnd. This capacitor must be placed as close as possible of the supply pins.

It is also important to take into consideration the Vref pin which is used to fix the output common mode voltage.

Effectively this pin must be driven by a low impedance voltage source and can be decoupled thanks to a 10 nF

bypass capacitor.

Larger bypass capacitor added on Vcc pin and Vref pin should help to enhance CMRR and PSRR performance.

6.10

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the current sensing, load and power

supply. It is good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.

When using shunt resistance lower than 1 Ω, it is important to use a 4-wire connection technique to sense

the current as described in the schematic below. Effectively, this technique allows to separate pairs of current

carrying and voltage-sensing electrodes to make more accurate measurements by eliminating the lead and

contact resistance from the measurement.

It is also important to treat the track connected to the input pin of the TSC21x as a differential pair; it must have

the same length and width, and ideally be placed on the same PCB plane, and above all must be routed as far

as possible from noisy source. As this track carries the input bias current, in a range of hundreds of µA, it can be

designed small but always by taking care of their resistivity. Any via in these input tracks are non-recommended to

avoid any parasitic resistance in this path.

To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top

layer ground planes together in many locations is often used.

A ground plane generally helps to reduce EMI, which is why it is generally recommended to use a multi-layer

PCB and use the ground planes as a shield to protect the internal track. In this case, pay attention to separate

the digital from the analog ground and avoid any ground loop. To further minimize EMI impact, it is important to

reduce loop area or antenna.

TSC210, TSC211, TSC212, TSC213, TSC214, TSC215

Improving precision

DS13237 - Rev 6

page 22/38