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©2020 Renesas Electronics Corporation

February 19, 2020

9SQL4952/9SQL4954/9SQL4958 Datasheet

1 The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads

section of the data sheet for the exact measurement setup. Values for the Common Clock architecture are calculated for CC/SRIS spread off and

spread on at -0.5%. SRIS values are calculated for CC/SRIS spread off and spread on at ≤-0.3%. If oscilloscope data is used, equipment noise is

removed from all results.

2 Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate

of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for

RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding

the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency.

For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case

where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used.

3 SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC

content.

4 Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.

5 Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.

6 While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide

specification limits, hence the N/A in the “Limit” column. SRIS values are informative only. In general, a clock operating in an SRIS system must be

twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by

√2. An

additional consideration is the value for which to divide by

√2. The conservative approach is to divide the ref clock jitter limit, and the case can be

made for dividing the channel simulation values by

√2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A

“rule-of-thumb” SRIS limit would be either 0.5ps RMS/

√2 = 0.35ps RMS, or 0.7ps RMS/√2 = 0.5ps RMS.

7 Calculated for Byte1[4:3] spread settings of 01, 10 and 11.

8 Calculated for Byte1[4:3] spread settings of 01, and 10.

Table 13. PCIe Phase Jitter of Differential Outputs

TAMB = over the specified operating range. Supply voltages per normal operation conditions. See Test Loads for loading conditions.

Parameter

Symbol

Conditions

Minimum

Typical

Maximum Limit

Units

Notes

PCIe Phase Jitter

(Common Clocked

Architecture)

tjphPCIeG1-CC

PCIe Gen1 (2.5 GT/s)

18

28

86

ps (p-p)

1,2,7

tjphPCIeG2-CC

PCIe Gen2 Hi Band (5.0 GT/s)

0.9

1.6

3

ps (RMS)

1,2,7

PCIe Gen2 Lo Band (5.0 GT/s)

0.4

0.6

3.1

ps (RMS)

1,2,

tjphPCIeG3-CC

PCIe Gen3 (8.0 GT/s)

0.25

0.4

1

ps (RMS)

1,2,3,7

tjphPCIeG4-CC

PCIe Gen4 (16.0 GT/s)

0.25

0.4

0.5

ps (RMS) 1,2,3,4,7

tjphPCIeG5-CC

PCIe Gen5 (32.0 GT/s)

0.09

0.11

0.15 ps (RMS) 1,2,3,5,7

PCIe Phase Jitter

(SRIS Architecture)

tjphPCIeG1-SRIS

PCIe Gen1 (2.5 GT/s)

4

6

N/A

ps (RMS)

1,2,6,8

tjphPCIeG2-SRIS

PCIe Gen2 (5.0 GT/s)

0.8

1.1

ps (RMS)

1,2,6,8

tjphPCIeG3-SRIS

PCIe Gen3 (8.0 GT/s)

0.3

0.4

ps (RMS)

1,2,6,8

tjphPCIeG4-SRIS

PCIe Gen4 (16.0 GT/s)

0.3

0.35

ps (RMS)

1,2,6,8

tjphPCIeG5-SRIS

PCIe Gen5 (32.0 GT/s)

0.15

0.19

ps (RMS)

1,2,6,8