FS32R274VCK2MMM datasheet(6/78 Pages) NXP

6 / 78 page

• 2 cycle delayed lockstep

• Harvard architecture with 64-bit bus for data and instructions

• Dual issue: up to two instructions per clock cycle

• 8 KB instruction cache and 4 KB data cache

• 64 KB data local memory

• with background load/store: backdoor access

• 0-wait state for all read and 32/64-bit write accesses

• Low number of wait states for backdoor accesses

• Support for decorated storage

• Variable Length Encoding (VLE) compliant for higher code density

• Single precision floating point operations

• Computation cores: Power Architecture® e200Z7 32-bit CPU

• Dual issue: up to two instructions per clock cycle

• Harvard architecture with 64-bit bus for data instructions

• 16 KB instruction cache and 16 KB data cache

• 64 KB data local memory

• with background load/store: backdoor access

• 0-wait state for all read and 32/64-bit write accesses

• Low number of wait states for backdoor accesses

• Support for decorated storage

• Using variable length encoding (VLE) for higher code density

• 4-way integer processing unit (SPE2)

• 2-way single-precision Floating Point Unit (EFPU2)

• 2 MB on-chip code flash (FMC flash) with ECC

• Three ports (one per CPU) shared between code and data flash with 4 × 256 bit

buffer for code and data flash including prefetch functions

• Data flash is part of the code flash module

• Including 64 KB EEPROM emulation

• 1.5 MB on-chip SRAM with ECC

• Decorated memory controller to support atomic read-modify-write operations

• Single- and double-bit error visibility is supported

• Up to four ports (one per CPU and SPT) and up to 8 banks allow simultaneous

accesses from different masters to different banks

• RADAR processing

• Signal Processing Toolbox (SPT) for RADAR signal processing acceleration

• Cross Timing Engine (CTE) for precise timing generation and triggering

• Waveform generation module (WGM) for chirp ramp generation

• 4x 12-bit

ΣΔ-ADC with 10 MSps (not supported on S32R264 devices)

• One DAC with 10 MSps (not supported on S32R264 devices)

• MIPICSI2 interface to connect external ADCs

Introduction

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VCK2MMM 数据表(PDF) 6 Page - NXP Semiconductors

FS32R274VCK2MMM 数据表(HTML) 6 Page - NXP Semiconductors

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