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FS32R274VCK2MMM 数据表(PDF) 60 Page - NXP Semiconductors |
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FS32R274VCK2MMM 数据表(HTML) 60 Page - NXP Semiconductors |
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60 / 78 page  Table 46. JTAG/CJTAG pin AC electrical characteristics 1 (continued) # Symbol Characteristic Min Max Unit 15 tBSDHT TCK Rising Edge to Boundary Scan Input Invalid 15 — ns 1. These specifications apply to JTAG boundary scan only. 2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions. Refer to pad specification for allowed transition frequency. 3. TMS timing is applicable only in CJTAG mode 4. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 5. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. TCK 1 2 2 3 3 Figure 32. JTAG test clock input timing Debug modules S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021 60 NXP Semiconductors |
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