Data Sheet

ADPA1122

THEORY OF OPERATION

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Rev. 0 | 14 of 17

The ADPA1122 is a GaN power amplifier that delivers 43 dBm (20

W) of pulsed power. The device consists of three cascaded gain

stages. A simplified block diagram is shown in Figure 46.

The pulsed bias voltage that applied to the VDD1, VDD2A, and

VDD3A pins provides bias to the drains of the first, second, and

third gain stages, respectively (a single common supply voltage

must be used). VDD2B and VDD3B are internally connected to

VDD2A and VDD3A, respectively, and are used as decoupling

nodes. The negative DC voltages applied to the VGG1 pin bias the

gates of the first, second, and third gain stages, respectively, to

allow control of the drain currents for each stage.

The recommended DC biasing results in a typical pulsed RF POUT

and PAE of 43.5 dBm and 46%, respectively, across the band of 9.6

GHz to 11 GHz when the input power is 22 dBm.

The ADPA1122 has single-ended RFIN and RFOUT ports that are

ac-coupled. The impedances of these ports are nominally 50 Ω

over the 8.2 GHz to 11.8 GHz operating frequency range. Conse-

quently, the ADPA1122 can be directly inserted into a 50 Ω system

without the need for external impedance matching components or

AC coupling capacitors.

A portion of the RF output signal (RFOUT) is directionally coupled

to a diode to detect the RF POUT. When the diode is DC biased, it

rectifies the RF power and makes it available as a DC voltage at

VDET. To allow temperature compensation of VDET, the reference

dc voltage detected through an identical diode that is not coupled to

the RF power is available on the VREF pin. The difference of VREF

− VDET provides a temperature compensated detector voltage that

is proportional to the RF POUT.

Figure 46. Basic Block Diagram