Data Sheet

ADPA1122

APPLICATIONS INFORMATION

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Rev. 0 | 15 of 17

BASIC CONNECTIONS

The basic connections for operating the ADPA1122 are shown in

Figure 47. Apply a power supply voltage between 24 V and 32 V to

the VDD1, VDD2A, and VDD3A pins. Decouple the VDD1, VDD2A,

VDD2B, VDD3A, and VDD3B pins with the capacitor and resistor

values shown in Figure 47. A single VGG1 pin is used to bias the

ADPA1122. Pin 5, Pin 9, Pin 11, and Pin 14 are designated as not

internally connected (NIC) pins. Although these NIC pins are not

internally connected, the NIC pins were all connected to ground

during the characterization of the device.

Apply a voltage between −4 V and −2 V to the VGG1 line to set

the bias level and drain current. Because the ADPA1122 cannot

support continuous operation, the device must be operated in

pulsed mode by pulsing either the gate voltage or the drain voltage.

In gate pulsed mode, VDD is held at a fixed level (nominally +28

V) while the gate voltage is pulsed between −4 V (off) and approxi-

mately −2.6 V (on). The exact on level can be adjusted to achieve

the desired quiescent drain current.

In drain pulsed mode, the VDD voltage is pulsed on and off while the

gate voltage is held at a fixed negative level between −4 V and −2

V. Because high currents and voltages are being switched on and

off, a metal-oxide semiconductor field effect transistor (MOSFET)

and a MOSFET switch driver are required in the circuit. Large

capacitors are also required, which act as local reservoirs of charge

and help provide the drain current required by the ADPA1122 while

maintaining a steady drain voltage during the on time of the pulse.

The ADPA1122-EVALZ evaluation board package includes a plugin

pulser board that contains the required circuitry to implement drain

pulsed mode. See the ADPA1122-EVALZ user guide for more

information.

To safely turn power on, VGG1 must be set to −4 V before the VDD

voltages are applied. After VGG1 is increased to achieve the desired

drain bias current, the RF input can be applied. Trigger the RF

source so that the RF is applied only during the time the drain pulse

is high. To safely turn power off, remove the RF input signal and

decrease VGG1 to −4 V. VDD can then be decreased to 0 V before

increasing VGG1 to 0 V.

Figure 47. Basic Connections