ST70134A

12/22

The information coming from the digital processor via the CTRLIN path is used to drive an 8-bit DAC

which generates a control current. This current is externally converted and filtered to generate the

required control voltage (range:-15V to 0.5V) for the varicap. The VCXO circuit characteristics are given

in Table 15.

N.B: frequency tuning range is proportional to the crystal dynamic capacitance Cm.

Figure 7 : Principle of VCXO control

The tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/LSB (8-bit).

The time constant of the tuning must be variable from 5s to 10s through an external capacitor Cs (R =

1M

Ω ±30%). This determines the speed of the VCXO in normal operation (slow speed in "show time")

with filtered VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt.

DIGITAL INTERFACE

Control Interface

The digital setting codes for the ST70134 configuration are sent over a serial line (CTRLIN) using the

word clock (CLWD).

The data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three LSBs being

used to identify the data contained in the 12 remaining bits.

Table 15 : VCXO circuit Characteristics

Symbol

Parameter

Minimum

Nominal

Maximum

Note

fabs

Absolute frequency accuracy

-15ppm

35.328MHz

+15ppm

frange

Frequency Tuning Range

±50ppm

IO

VCXO Output Current

100

µA

Rref = 16.5k

Ω

AVDD = 3.3V

Ii

Reference Input Current

100

µA

1mA

AVDD = 3.3V

DAC

8 Bits

1M

Ω

±30%

Filtered VCXO

(see CTRLIN table)

44

VCOC

Cs

AVDD

7

CTRLIN

55

IVCO

AVDD

Rref

AVDD/22 ÷ AVDD/2

li

56

VCXO

Clk35

60

59

Cp

XTALI

XTALO

Ct

Rt

AGND

Io = li

-15V