ST70134A

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RX Signal Dynamic

The dynamic of the signal from the ADC is limited to 13bits. Those bits are converted to a signed (2’s

complement) representation with a maximal positive number of 214 -1 and a most negative number -214.

The 2 LSBs are filled with ’0’.

The two sign bits must be identical.

Table 20 : RX Data Bit Map

BIT MAP/NIBBLE

N0

N1

N2

N3

RXD0

0

data bit 2

data bit 6

data bit 10

RXD1

0

data bit 3

data bit 7

data bit 11

RXD2

d0 = data bit 0 (LSB)

data bit 4

data bit 8

data SIGN

RXD3

data bit 1

data bit 5

data bit 9

data SIGN

Table 21 : RX Nibble Bit Map

N3

N2

N1

N0

sign

sign

d11

d10

d9

d8

d7

d6

d5

d4

d3

d2

d1

d0

0

0

Figure 9 : TX/ RX Digital Interface Timing

CLKM

35.328MHz

CLWD

8.832MHz

TXDx/RXDx

N0

N1

N2

N3

OSR = 4

CLKNIB

17.664MHz

CLWD

4.4162MHz

TXDx/RXDx

N0

N1

N2

N3

OSR = 2