©2019 Integrated Device Technology, Inc.

SEPTEMBER 2019

DSC-2691/17

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HIGH SPEED

2K X 8 DUAL-PORT

STATIC RAM

WITH INTERRUPTS

71321SA/LA

71421SA/LA

Features

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High-speed access

– Commercial: 20/35/55ns (max.)

– Industrial: 25/55ns (max.)

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Low-power operation

– IDT71321/IDT71421SA

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71321/421LA

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

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Two INT flags for port-to-port communications

Functional Block Diagram

NOTES:

1. IDT71321(MASTER):BUSYisopendrainoutputandrequirespullupresistorof270

Ω.

IDT71421 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor of 270

Ω.

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MASTER IDT71321 easily expands data bus width to 16-or-

more-bits using SLAVE IDT71421

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On-chip port arbitration logic (IDT71321 only)

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BUSY output flag on IDT71321; BUSY input on IDT71421

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Fully asynchronous operation from either port

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Battery backup operation – 2V data retention (LA only)

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TTL-compatible, single 5V ±10% power supply

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Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and

64-Pin STQFP

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Industrial temperature range (–40°C to +85°C) is available

for selected speeds

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Green parts available, see ordering information

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address

Decoder

I/O

Control

R/

WL

CEL

OEL

BUSYL

A10L

A0L

2691 drw 01

I/O0L- I/O7L

CEL

OEL

R/

WL

INTL

BUSYR

I/O0R-I/O7R

A10R

A0R

INTR

CER

OER

(2)

(1,2)

(1,2)

(2)

R/

WR

CER

OER

R/

WR

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