6.42

71321SA/LA and 71421SA/LA

High Speed 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

16

beingexpandedindepth,thentheBUSYindicationfortheresultingarray

does not require the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one

master part is used to decide which side of the SRAM array will receive

aBUSYindication,andtooutputthatindication.Anynumberofslavesto

be addressed in the same address range as the master, use the BUSY

signalasawriteinhibitsignal.ThusontheIDT71321/IDT71421SRAMs

theBUSYpinisanoutputifthepartisMaster(IDT71321),andtheBUSY

pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The BUSY arbitration, on a Master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupted data in the slave.

Functional Description

The IDT71321/IDT71421 provides two ports with separate control,

addressandI/Opinsthatpermitindependentaccessforreadsorwrites

to any location in memory. The IDT71321/IDT71421 has an automatic

power down feature controlled by CE. The CE controls on-chip power

downcircuitrythatpermitstherespectiveporttogointoastandbymode

whennotselected(CE=VIH).Whenaportisenabled,accesstotheentire

memoryarrayispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 7FE

(HEX), whereawriteisdefinedastheCER =R/WR=VIL,perTruthTable

II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen

CEL = OEL = VIL,R/W is a "don't care". Likewise, the right port interrupt

flag (INTR) is asserted when the left port writes to memory location 7FF

(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe

memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,

sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,

address locations 7FE and 7FF are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

Busy Logic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

TheBUSY pincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesabusyindication,thewritesignalisgatedinternally

to prevent the write from proceeding.

TheuseofBUSYLogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.InslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT71321 (Master) are open drain type

outputsandrequireopendrainresistorstooperate.IftheseSRAMsare

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.

2691 drw 16

MASTER

Dual Port

SRAM

BUSYL

BUSYR

CE

MASTER

Dual Port

SRAM

BUSYL

BUSYR

CE

SLAVE

Dual Port

SRAM

BUSYL

BUSYR

CE

SLAVE

Dual Port

SRAM

BUSYL

BUSYR

CE

BUSYL

BUSYR

5V

5V

270

Ω

270

Ω