P87LPC767FD datasheet(21/60 Pages) PHILIPS

21 / 60 page

Philips Semiconductors

Product data

87LPC767

Low power, low price, low pin count (20 pin)

microcontroller with 4-kbyte OTP and 8-bit A/D converter

2001 Aug 07

BIT

SYMBOL

FUNCTION

I2CFG.7

SLAVEN

Slave Enable. Writing a 1 this bit enables the slave functions of the I2C subsystem. If SLAVEN and

MASTRQ are 0, the I2C hardware is disabled. This bit is cleared to 0 by reset and by an I2C

time-out.

I2CFG.6

MASTRQ

Master Request. Writing a 1 to this bit requests mastership of the I2C bus. If a transmission is in

progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. A

start condition is sent and DRDY is set (thus making ATN = 1 and generating an I2C interrupt).

When a master wishes to release mastership status of the I2C, it writes a 1 to XSTP in I2CON.

MASTRQ is cleared by an I2C time-out.

I2CFG.5

CLRTI

Writing a 1 to this bit clears the Timer I overflow flag. This bit position always reads as a 0.

I2CFG.4

TIRUN

Writing a 1 to this bit lets Timer I run; a zero stops and clears it. Together with SLAVEN, MASTRQ,

and MASTER, this bit determines operational modes as shown in Table 1.

I2CFG.2, 3

—

Reserved for future use. Should not be set to 1 by user programs.

I2CFG.1, 0 CT1, CT0

These two bits are programmed as a function of the CPU clock rate, to optimize the MIN HI and LO

time of SCL when this device is a master on the I2C. The time value determined by these bits

controls both of these parameters, and also the timing for stop and start conditions.

CT0

SU01157

CT1

—

TIRUN

CLRTI

MASTRQ

SLAVEN

I2CFG

Reset Value: 00h

Not Bit Addressable

Address: C8h

Figure 10. I2C Configuration Register (I2CFG)

Regarding Software Response Time

Because the 87LPC767 can run at 20 MHz, and because the I2C

interface is optimized for high-speed operation, it is quite likely that

an I2C service routine will sometimes respond to DRDY (which is set

at a rising edge of SCL) and write I2DAT before SCL has gone low

again. If XDAT were applied directly to SDA, this situation would

produce an I2C protocol violation. The programmer need not worry

about this possibility because XDAT is applied to SDA only when

SCL is low.

Conversely, a program that includes an I2C service routine may take

a long time to respond to DRDY. Typically, an I2C routine operates

on a flag-polling basis during a message, with interrupts from other

peripheral functions enabled. If an interrupt occurs, it will delay the

response of the I2C service routine. The programmer need not worry

about this very much either, because the I2C hardware stretches the

SCL low time until the service routine responds. The only constraint

on the response is that it must not exceed the Timer I time-out.

Values to be used in the CT1 and CT0 bits are shown in Table 2. To

allow the I2C bus to run at the maximum rate for a particular

oscillator frequency, compare the actual oscillator rate to the fOSC

max column in the table. The value for CT1 and CT0 is found in the

first line of the table where CPU clock max is greater than or equal

to the actual frequency.

Table 2 also shows the machine cycle count for various settings of

CT1/CT0. This allows calculation of the actual minimum high and

low times for SCL as follows:

SCL min high low time (in microseconds)

+ 6 * Min Time Count

CPU clock (in MHz)

For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the

minimum SCL high and low times will be 5.25

µs.

Table 2 also shows the Timer I timeout period (given in machine

cycles) for each CT1/CT0 combination. The timeout period varies

because of the way in which minimum SCL high and low times are

measured. When the I2C interface is operating, Timer I is pre-loaded

at every SCL transition with a value dependent upon CT1/CT0. The

pre-load value is chosen such that a minimum SCL high or low time

has elapsed when Timer I reaches a count of 008 (the actual value

pre-loaded into Timer I is 8 minus the machine cycle count).

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