RA4E2 datasheet(32/90 Pages) RENESAS

32 / 90 page

PLLCR.PLLSTP

OSCSF.PLLSF

PLL clock

tPLLWT

PLL circuit output

Figure 2.10

PLL clock oscillation start timing

Sub-clock oscillator output

SOSCCR.SOSTP

Sub-clock

tSUBOSCWT

Figure 2.11

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.19

Reset timing

Parameter

Symbol Min Typ Max

Unit Test conditions

RES pulse width

Power-on

tRESWP 0.7 —

—

Figure 2.12

Deep Software Standby mode

tRESWD 0.6 —

—

Figure 2.13

Software Standby mode, Subosc-speed

mode

tRESWS 0.3 —

—

All other

tRESW

200 —

—

µs

Wait time after RES cancellation

tRESWT —

37.3 41.2

µs

Figure 2.12

Wait time after internal reset cancellation

(IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error

reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset)

tRESW2 —

324 397.7 µs

—

RA4E2 Datasheet

2. Electrical Characteristics

R01DS0413EJ0110 Rev.1.10

Feb 28, 2023

Page 32 of 90

RA4E2 数据表(PDF) 32 Page - Renesas Technology Corp

RA4E2 数据表(HTML) 32 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载