RA4E2 datasheet(85/90 Pages) RENESAS

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Table 3.1

Peripheral base address (2 of 2)

Name

Description

Base address

USBFS

USB 2.0 FS Module

0x4009_0000

SSIE0

Serial Sound Interface Enhanced (SSIE)

0x4009_D000

CEC

Consumer Electronics Control

0x400A_C000

CANFD

CANFD Module Control

0x400B_0000

PSCU

Peripheral Security Control Unit

0x400E_0000

AGT0

Low Power Asynchronous General purpose Timer 0

0x400E_8000

AGT1

Low Power Asynchronous General purpose Timer 1

0x400E_8100

TSN

Temperature Sensor

0x400F_3000

CRC

CRC Calculator

0x4010_8000

DOC

Data Operation Circuit

0x4010_9000

SCI0

Serial Communication Interface 0

0x4011_8000

SCI9

Serial Communication Interface 9

0x4011_8900

SPI0

Serial Peripheral Interface 0

0x4011_A000

SPI1

Serial Peripheral Interface 1

0x4011_A100

I3C

I3C Bus Interface

0x4011_F000

CANFD ECC

0x4012_F000

GPT16E0

General PWM 16-Bit Timer 0 (16-bit Enhanced High Resolution)

0x4016_9000

GPT16E1

General PWM 16-Bit Timer 1 (16-bit Enhanced High Resolution)

0x4016_9100

GPT16E4

General PWM 16-Bit Timer 4 (16-bit Enhanced High Resolution)

0x4016_9400

GPT16E5

General PWM 16-Bit Timer 5 (16-bit Enhanced High Resolution)

0x4016_9500

GPT_OPS

Output Phase Switching Controller

0x4016_9A00

ADC120

12bit A/D Converter 0

0x4017_0000

DAC12

12-bit D/A converter

0x4017_1000

FLAD

Data Flash

0x407F_C000

FACI

Flash Application Command Interface

0x407F_E000

Note:

Name = Peripheral name

Description = Peripheral functionality

Base address = Lowest reserved address or address used by the peripheral

3.2

Access Cycles

This section provides access cycle information for the I/O registers described in this manual.

● Registers are grouped by associated module.

● The number of access cycles indicates the number of cycles based on the specified reference clock.

● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations

cannot be guaranteed.

● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization

cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio

between ICLK and PCLK.

● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always

constant.

● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided

clock synchronization cycles.

● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.

RA4E2 Datasheet

Appendix 3. I/O Registers

R01DS0413EJ0110 Rev.1.10

Feb 28, 2023

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