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数据搜索系统，热门电子元器件搜索 |
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FS6407 数据表(PDF) 39 Page - NXP Semiconductors |
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FS6407 数据表(HTML) 39 Page - NXP Semiconductors |
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39 / 111 page  NXP Semiconductors 39 FS6407/FS6408 6.5.3.1 RST error counter at start-up or resuming from LPOFF mode At start-up or when resuming from LPOFF mode the reset error counter starts at level 1 and FS0B is asserted low. To remove the activation of FS0B, the RST error counter must go back to value “0” (seven consecutive good watchdog refresh decreases the reset error counter down to 0) and a right command is sent to FS_OUT register (Figure 20). Figure 18. Example of WD operation generating a reset (WD_error_cnt = 6) Figure 19. Example of WD operation leading a decrement of the reset error counter (WD_resfresh_cnt = 6) WD window OK NOK NOK OK 0 2 WD error counter 4 3 NOK 5 OK 4 6 NOK Reset error counter 1 RSTB 0 10 WD Refresh counter 00 1 1 0 RSTb delay time 1st WD refresh OK after INIT phase. Start of the WD window New fully OPEN window of 256 ms 6 2 0 OK OK OK OK OK OK OK 0 OK 1 2 3 4 5 6 0 1 1 WD window WD error counter Reset error counter RSTb WD Refresh counter RSTb delay time 1 NOK New fully OPEN window of 256 ms 4 |
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