FS6407 datasheet(40/111 Pages) NXP

40 / 111 page

NXP Semiconductors

FS6407/FS6408

Figure 20. Reset error counter and FS0B deactivation sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6)

6.5.4

Fail-safe output (FS0B) deactivation

When the fail-safe output FS0B is asserted low by the device due to a fault, some conditions must be validated before allowing the FS0B

pin to be deactivated by the device. These conditions are:

• Fault is removed

• Reset error counter must be at “0”

• FS_OUT register must be filled with the right value.

6.5.4.1

Faults triggering FS0B activation

The activation of the FS0B is clearly dependent on the product configuration, but the following items can be settled:

• IO_01/IO_23/IO_45 error detection

• Undervoltage

•Overvoltage

• IO_1 FB_Core Delta

• Analog BIST fail (not configurable)

• SPI DED (not configurable)

• RSTB shorted to high (not configurable)

• RSTB error counter level

6.5.5

SPI DED

Some SPI registers affect some safety critical aspects of the fail-safe functions, and thus are required to be protected against SEU (Single

Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open.

Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content.

At this stage, if there is 1 single bit flip, the detection is made due to hamming code, and the error is corrected automatically (fully

transparent for the user), and a flag is sent. If there are two errors (DED - Dual Error Detection), the detection is made due to hamming

code but detected errors cannot be corrected. The flag is sent, RSTB and FS0B are activated.

6.5.6

FS_OUT register

When the fault is removed and the reset error counter changes back to level “0”, a right word must be filled in the FS_OUT register. The

value is dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied.

Figure 21. FS_OUT register based on LFSR value

RSTb

Reset error counter

RST_ERR_CNT

FS0b

# WD refresh counter max value +1

consecutive WD answers OK

FS_OUT

write OK

Output stage ON

OFF

WD error counter

= 6

WD error counter

= 6

WD error counter

= 6

Reset delay

# WD refresh counter max value +1

consecutive WD answers OK

OFF

FS_OUT

write OK

WD_LFSR_7:0=

FS_OUT_7:0 =

b0b1b2b3b4b5b6b7

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