841S012DI Datasheet

©2016 Integrated Device Technology, Inc

January 4, 2016

10

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. To achieve optimum jitter per-

formance, power supply isolation is required. The 841S012DI

provides separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

DD

, V

DDA

, V

DDOB

, and

V

DDOC

should be individually connected to the power supply

plane through vias, and 0.01µF bypass capacitors should be

used for each pin. Figure 1 illustrates this for a generic V

DD

pin

and also shows that V

DDA

requires that an additional10

Ω resistor

along with a 10µF bypass capacitor be connected to the V

DDA

pin.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

INPUTS:

CRYSTAL INPUTS

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k

Ω resistor can be tied

from XTAL_IN to ground.

REF_IN INPUT

For applications not requiring the use of the reference clock,

it can be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the REF_IN to ground.

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUTS

All unused LVCMOS output can be left floating. We recommend that

there is no trace attached.

DIFFERENTIAL OUTPUTs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.