LT1725IGN datasheet(10/28 Pages) LINER

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LT1725

1725f

OPERATIO

Enable Delay

When the output switch shuts off, the flyback pulse

appears. However, it takes a finite time until the trans-

former primary side voltage waveform approximately rep-

resents the output voltage. This is partly due to rise time

on the MOSFET drain node, but more importantly, due to

transformer leakage inductance. The latter causes a volt-

age spike on the primary side not directly related to output

voltage. (Some time is also required for internal settling of

the feedback amplifier circuitry.)

In order to maintain immunity to these phenomena, a

fixed delay is introduced between the switch turnoff

command and the enabling of the feedback amplifier. This

is termed “enable delay”. In certain cases where the

leakage spike is not sufficiently settled by the end of the

enable delay period, regulation error may result. See

Applications Information for further details.

Collapse Detect

Once the feedback amplifier is enabled, some mechanism

is then required to disable it. This is accomplished by a

collapse detect comparator, which compares the flyback

voltage (FB referred) to a fixed reference, nominally 80%

of VBG. When the flyback waveform drops below this

level, the feedback amplifier is disabled. This action

accommodates both continuous and discontinuous mode

operation.

Minimum Enable Time

The feedback amplifier, once enabled, stays enabled for a

fixed minimum time period termed “minimum enable

time.” This prevents lockup, especially when the output

voltage is abnormally low, e.g., during start-up. The mini-

mum enable time period ensures that the VC node is able

to “pump up” and increase the current mode trip point to

the level where the collapse detect system exhibits proper

operation. The “minimum enable time” often determines

the low load level at which output voltage regulation is lost.

See Applications Information for details.

Effects of Variable Enable Period

It should now be clear that the flyback amplifier is enabled

during only a portion of the cycle time. This can vary from

the fixed “minimum enable time” described to a maximum

of roughly the “off” switch time minus the enable delay

time. Certain parameters of flyback amp behavior will then

be directly affected by the variable enable period. These

include effective transconductance and VC node slew rate.

LOAD COMPENSATION THEORY

The LT1725 uses the flyback pulse to obtain information

about the isolated output voltage. A potential error source

is caused by transformer secondary current flow through

the real life nonzero impedances of the output rectifier,

50k

VIN

LOAD

COMP I

VBG

Q1 Q2

ROCMP

RCMPC

RSENSE

ISENSE

1725 F01

–

Figure 1. Load Compensation Diagram

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