AD8311

Rev. 0 | Page 13 of 24

First, the summed detector currents are written as a function of

the input power.

INT

IN

SLP

DET

I

P

I

I

+

×

=

(3)

where:

state average value is extracted through the subsequent

integration step.

dependent on the RF waveform (not the envelope). Assuming

a sinusoidal input,

The current generated by the setpoint interface is simply

SET

SET

SET

R

V

I

=

(4)

where the

helpful in improving the phase margin at low powers where the

PA control gain (that is,

that the voltage appearing on this capacitor,

integral of the difference current.

() (

)

FLT

DET

SET

FLT

sC

I

I

s

V

−

=

(5)

FLT

INT

IN

SLP

SET

SET

sC

I

P

I

R

V

−

×

−

=

(6)

of the output buffer is ×1.35, plus a slight offset voltage. The

AD8311 seeks to drive the RF power to its maximum value

whenever it falls below the setpoint. The use of exact integration

results in a dc error that is theoretically zero, and the logarithmic

detection law would ideally result in a constant response time

following a step change of either the setpoint or the power level if

the power-amplifier control function were likewise linear-in-dB.

This latter condition is rarely true, however, and it follows that in

practice the loop response time depends on the power level. This

effect can strongly influence the design of the control loop.

Equation 6 can be restated as

()

sT

V

P

V

V

s

V

INT

IN

SLP

SET

APC

−

×

−

=

(7)

where:

value of 1.44 V.

T is the effective time constant for the integration and is equal

voltage gain of the buffer.

So the open-loop integration time constant can be written as

35

.

1

FLT

SET

OpenLoop

C

R

T

×

=

(8)

To assess the closed-loop performance, refer to the block

diagram in Figure 28 and calculate the loop transfer function.

very high PA control function gains (> than 500 dB/V) and/or

very wide PA control port bandwidths. Assuming that the

frequency response of the output buffer and the log amp can be

neglected, the overall transfer function can be expressed as

[

]

()

(

)

()

()

[]

FLT

PA

PA

SLP

FLT

PA

PA

INT

SLP

SET

sC

s

G

I

sC

s

G

I

I

I

τ

+

×

×

+

×

τ

+

×

×

−

×

+

1

35

.

1

1

)

1

(

1

35

.

1

30

(9)

dB/V, and the factor of −30 is due to the coupler.

Equation 9 assumes that the next parasitic pole in the control

loop comes from the PA. For a typical PA, a 1 MHz pole is not

unusual, making this a good assumption. Therefore, except for

in the case of a very wide bandwidth on the PA control port

(>10 MHz), the response time and stability of the control loop is

mainly determined by the characteristics of the PA. This is true

for both the gain and the phase response. It is essential to

understand both the magnitude and frequency response of the

power amplifier control port.

1

+

1.35

s

τ

BUFFER

1 +

1 + s

τ

PA

–30dB

COUPLER

1 + s

τ

LOGAMP

+

_

Figure 28. Control Loop Block Diagram