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AD8311

Rev. 0 | Page 16 of 24

Some of the output power from the PA is coupled off using a

dual-band directional coupler (Murata part number

LDC15D190A0007A). This has a coupling factor of

approximately +19 dB for the GSM band and +14 dB for DCS

and an insertion loss of 0.38 dB and 0.45 dB, respectively.

Because the PF08107B transmits a maximum power level of

+35 dBm for GSM and +32 dBm for DCS, additional

attenuation of 20 dB is required before the coupled signal is

applied to the AD8311. This results in peak input levels to the

AD8311 of −4 dBm (GSM) and −2 dBm (DCS). While the

AD8311 gives a linear response for input levels up to +2 dBm,

for highly temperature-stable performance at maximum PA

output power the maximum input level should be limited to

approximately −2 dBm (see Figure 5 and Figure 7). This does,

however, reduce the sensitivity of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V,

is applied to the VSET pin of the AD8311. This typically is

supplied by a DAC. The AD8311’s VAPC output drives the level

control pin of the power amplifier directly. VAPC reaches a

maximum value of approximately 2.5 V on a 2.7 V supply while

delivering the 3 mA required by the level control input of the

PA. This is more than sufficient to exercise the gain control

range of the PA.

During initialization and completion of the transmit sequence,

VAPC should be held at its minimum level of 300 mV by keeping

VSET below 150 mV.

In this example, VSET is supplied by an 8-bit DAC that has an

output range from 0 V to 2.55 V or 10 mV per bit. This sets the

control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times

10 mV). If finer resolution is required, the DAC’s output voltage

can be scaled using two resistors as shown. This converts the

DAC’s maximum voltage of 2.55 V down to 1.6 V and increases

the control resolution to 0.25 dB/bit.

A filter capacitor (CFLT) must be used to stabilize the loop. The

choice of CFLT depends to a large degree on the gain control

dynamics of the power amplifier, something that is frequently

poorly characterized, so some trial and error might be

necessary.

In this example, a 150 pF capacitor is used and a 1.5 kΩ series

resistor is included. This adds a zero to the control loop and

increases the phase margin, which helps to make the step

response of the circuit more stable when the PA output power is

low and the slope of the PA’s power control function is the

steepest.

A smaller filter capacitor can be used by inserting a series

resistor between VAPC and the control input of the PA. A series

resistor works with the input impedance of the PA to create a

resistor divider, which reduces the loop gain. The size of the

resistor divider ratio depends on the available output swing of

VAPC and the required control voltage on the PA.

This technique can also be used to limit the control voltage in

situations where the PA cannot deliver the power level being

demanded by VAPC. Overdrive of the control input of some

PAs causes increased distortion. It should be noted, however,

that if the control loop opens (that is, VAPC goes to its maximum

value in an effort to balance the loop), the quiescent current of

the AD8311 increases somewhat, particularly at supply voltages

greater than 3 V.

Figure 32 shows the relationship between VSET and output

power (POUT) at 0.9 GHz. The overall gain control function is

linear in dB for a dynamic range of over 40 dB. Note that for

VSET voltages below 300 mV, the output power drops off steeply

as VAPC drops toward its minimum level of 300 mV.

–20

1.6

SETPOINT VOLTAGE (V)

–10

0.2

0.4

0.6

0.8

1.0

1.2

1.4

–3

–1

–2

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

Figure 32. POUT vs. VSET at 0.9 GHz for Dual Mode Handset

Power Amplifier Application;

−40°C, +25°C, and +85°C

POWER-ON AND POWER-OFF

The AD8311 can be completely disabled by pulling the supply

voltage to ground. The voltage on VSET should be kept below

150 mV during power-on and power-off to prevent any

unwanted transients on VAPC.

INPUT COUPLING OPTIONS

The internal 5 pF coupling capacitor of the AD8311 and the low

frequency input impedance of 2.14 kΩ give a high-pass input

corner frequency of approximately 16 MHz. This sets the

minimum operating frequency. Figure 33, Figure 34, and

Figure 35 shows three options for input coupling. A broadband

resistive match can be implemented by connecting a shunt

resistor to ground at RFIN (Figure 33). This 52.3 Ω resistor

(other values can also be used to select different overall input

impedances) combines with the input impedance of the

AD8311 to give a broadband input impedance of 50 Ω. While

the input resistance and capacitance (CIN and RIN) of the

AD8311 vary from device to device by approximately ±20%, as

well as in the same device over a range of frequencies

(Figure 14), the dominance of the external shunt resistor means

that the variation in the overall input impedance is close to the

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