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ICS9LPR501 数据表(PDF) 9 Page - Renesas Technology Corp |
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ICS9LPR501 数据表(HTML) 9 Page - Renesas Technology Corp |
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9 / 22 page  IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 Advance Information ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR 9 Datasheet Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDI TI ON S MIN TYP MAX UNITS NOTES Lo ng Accuracy ppm see Tperiod min-max values -100 0 1 00 ppm 1,2 33.33MHz outpu t no spread 29.9 9700 30.00300 ns 2 33.33MHz output spread 30.0 8421 30.23459 ns 2 33.33MHz outpu t no spread 29.4 9700 30.50300 ns 2 33.33MH z o utput nominal/spread 29.5 6617 30.58421 ns 2 Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 1.71 4 V/ns 1 Falling Edge Sle w Rate t FLR Measured from 2.0 to 0.8 V 1 1.78 4 V/ns 1 Pin to Pin Skew tske w VT = 1.5 V 2 50 ps 2 Intential PCI to PCI de lay tskew VT = 1.5 V 100 187 3 00 ps 2 Duty C ycle d t1 V T = 1.5 V 45 51 55 % 2 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 103 5 00 ps 2 Clock period T per io d Absolute min/max period T abs Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz PARAMETER SYMBOL CONDI TI ON S MIN TYP MAX UNITS NOTES Lo ng Accuracy ppmsee Tperiod min-max values -100 0 1 00 ppm2,4 Clock period Tperio d 48.0 0MHz output n ominal 20.83125 20 .83542 ns 2,3 Absolute min/max period Tabs 48.0 0MHz output n ominal 20.48125 21 .18542 ns 2 CLK High Time THI GH 8.216563 11 .15198 V CLK Low time T LOW 7.816563 10 .95198 V Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 1.2 2 V/ns 1 Falling Edge Sle w Rate tFLR Measured from 2.0 to 0.8 V 1 1.3 2 V/ns 1 Duty C ycle dt1 VT = 1.5 V 45 50.8 % 55 %2 Jitter, Cycle to cycle t jcyc- cyc V T = 1.5 V 132. 2 3 50 ps 2 Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN TYP M AX UNITS Notes Lo ng Accuracy ppmsee Tperiod min-max values -100 0 1 00 ppm2, 4 Clock period Tperiod 14.318MHz output nominal 69.82033 69 .86224 ns 2, 3 Absolute min/max period Tabs 14.318MHz output nominal 69.83400 70 .84800 ns 2 C LK High Time THIGH 29.97543 38 .46654 V CLK Low time TLOW 29.57543 38 .26654 V Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 1.4 4 V/ns 1 Falling Edge Sle w Rate tFLR Measured from 2.0 to 0.8 V 1 1.7 4 V/ns 1 Duty C ycle dt 1 VT = 1.5 V 45 53.1 55 % 2 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 138 1000 ps 2 |
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