IDTTM/ICSTM

64-pin CK505 w/Fully Integrated Voltage Regulator

1118N—05/19/11

Advance Information

ICS9LPR501

64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

10

Datasheet

Electrical Characteristics - SE1/2=25MHz

PARAMETER

SYMBOL

CONDI TI ON S

MIN

TYP

MAX

UNITS

NOTES

Lo ng Accuracy

ppmsee Tperiod min-max values

-100

0

1 00

ppm1,2

Clock period

Tperio d

25.0 0MHz output n ominal

39.99600

40 .00400

ns

1

Absolute min/max period

T

abs

25.0 0MHz output n ominal

39.32360

40 .67640

ns

1

Rising Edge Slew Rate

tSLR

Measured from 0.8 to 2.0 V

1

1.2

2

V/ns

1

Falling Edge Sle w Rate

t

FLR

Measured from 2.0 to 0.8 V

1

1.3

2

V/ns

1

Duty C ycle

d

t1

V

T = 1.5 V

45

50.8

55

%1

Jitter, Cycle to cycle

tjcyc-cyc

VT = 1.5 V

60

500

ps

1

Jitter, Long Term

t

LT J

V

T = 1.5 V @ 10us de lay

780

1000

ps

1

1

Edge rate in system is measured from 0.8V to 2.0V.

2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V

3 The average period over any 1us period of time

4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz

NOTES on SE outputs: (unless otherwise noted, guara nteed by design and characterization, not 100% tested in production).

FSLC

2

B0b7

FSLB

1

B0b6

FSLA

1

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

0

0

0

266.66

0

0

1

133.33

0

1

0

200.00

0

1

1

166.66

1

0

0

333.33

1

0

1

100.00

1

1

0

400.00

11

1

1. FS

LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS

LC is a three-level input. Please see the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

Table 1: CPU Frequency Select Table

96.00

Reserved

100.00

33.33

14.318

48.00

Pin 17

Pin 18

Spread

MHz

MHz

%

00

0

0

0

0

0

1

100.00

100.00

0.5% Down Spread

SRCCLK1 from SRC_MAIN

0

0

1

0

100.00

100.00

0.5% Down Spread

Only SRCCLK1 from PLL3

0

0

1

1

100.00

100.00

1% Down Spread

Only SRCCLK1 from PLL3

0

1

0

0

100.00

100.00

1.5% Down Spread

Only SRCCLK1 from PLL3

0

1

0

1

100.00

100.00

2% Down Spread

Only SRCCLK1 from PLL3

0

1

1

0

100.00

100.00

2.5% Down Spread

Only SRCCLK1 from PLL3

01

1

1

N/A

N/A

N/A

N/A

1

0

0

0

24.576

24.576

None

24.576Mhz on SE1 and SE2

1

0

0

1

24.576

98.304

None

24.576Mhz on SE1, 98.304Mhz on SE2

1

0

1

0

98.304

98.304

None

98.304Mhz on SE1 and SE2

1

0

1

1

27.000

27.000

None

27Mhz on SE1 and SE2

1

1

0

0

25.000

25.000

None

25Mhz on SE1 and SE2

11

0

1

N/A

N/A

N/A

N/A

11

1

0

N/A

N/A

N/A

N/A

11

1

1

N/A

N/A

N/A

N/A

Comment

PLL 3 disabled

B1b1

B1b4

B1b3

B1b2

Table 2: PLL3 Quick Configuration