9

Integrated

Circuit

Systems, Inc.

ICS9LPRS511

Advance Information

1137—09/05/08

I2C Table: Output Control Register

Byte 5

Name

Control Function

PWD

A/B/C/D/E/H/J

Bit 7

24_48Mhz

Output Control

RW

1

Bit 6

Diff AMP

RW

1

Bit 5

Diff AMP

RW

0

Bit 4

Reserved

Reserved

RW

0

Bit 3

iAMT EN (only

applicable to revisions

H and J, otherwise

this is a reserved bit)

iAMT Enable Control

RW

0

Bit 2

Reserved

Reserved

RW

0

Bit 1

Reserved

Reserved

RW

0

Bit 0

Load Control

IIC Load control

RW

0

I2C Table: Reserved Register

Byte 6

Name

Control Function

Type

PWD

A/B/C/D/E/H/J

Bit 7

Reserved

Reserved

RW

0

Bit 6

Reserved

Reserved

RW

0

Bit 5

Reserved

Reserved

RW

0

Bit 4

Reserved

Reserved

RW

0

Bit 3

Reserved

Reserved

RW

0

Bit 2

Reserved

Reserved

RW

0

Bit 1

Reserved

Reserved

RW

0

Bit 0

Reserved

Reserved

RW

0

Stoppable

--

-

Free-running

Load

Disable

Enable

-

0

-

Do not Load

-

-

-

--

01 = 900mV

10 = 800mV

11 = 700mV

-

1

--

-

--

-

-

-

-

-

Differential output

Amplitude Control

00 = 600mV

01

I2C Table: Revision and Vendor ID Register

Byte 7

Name

Control Function

Type

PWD

A/B

PWD

C/D

PWD

E

PWD

H

PWD

J

Bit 7

RID3

R

00

0

0

0

Bit 6

RID2

R

00

1

1

1

Bit 5

RID1

R

01

0

0

1

Bit 4

RID0

R

00

0

1

0

Bit 3

VID3

R

00

0

0

0

Bit 2

VID2

R

00

0

0

0

Bit 1

VID1

R

00

0

0

0

Bit 0

VID0

R

11

1

1

1

01

-

--

001 = ICS

-

Revision ID

--

--

-

-

--

VENDOR ID

-

--

I2C Table: Byte Count Register

Byte 8

Name

Control Function

Type

PWD

A/B/C/D/E/H/J

Bit 7

BC7

R

0

Bit 6

BC6

R

0

Bit 5

BC5

R

0

Bit 4

BC4

RW

0

Bit 3

BC3

RW

1

Bit 2

BC2

RW

1

Bit 1

BC1

RW

1

Bit 0

BC0

RW

1

I2C Table: Watch Dog Timer Control Register

Byte 9

Name

Control Function

Type

PWD

A/B/C/D/E/H/J

Bit 7

HWD_EN

Watchdog Hard Alarm

Enable

RW

0

Bit 6

SWD_EN

Watchdog Soft Alarm

Enable

RW

0

Bit 5

WD Hard Status

WD Hard Alarm Status

R

X

Bit 4

WD Soft Status

WD Soft Alarm Status

R

X

Bit 3

WDTCtrl

Watch Dog Alarm Time

base Control

RW

0

Bit 2

HWD2

WD Hard Alarm Timer Bit 2

RW

1

Bit 1

HWD1

WD Hard Alarm Timer Bit 1

RW

1

Bit 0

HWD0

WD Hard Alarm Timer Bit 0

RW

1

Disable

0

Writing to this register will configure how many bytes will be

read back, default is 0F = 15 bytes.

1

1

0

Enable

Normal

These bits represent X*290ms (or 1.16S) the watchdog timer

waits before it goes to alarm mode. Default is 7 X 290ms =

2s.

1160ms Base

Disable

Normal

Alarm

Byte Count Programming

b(7:0)

290ms Base

Enable

Alarm