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ICS9LPRS511 数据表(PDF) 10 Page - Renesas Technology Corp |
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ICS9LPRS511 数据表(HTML) 10 Page - Renesas Technology Corp |
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10 / 20 page  10 Integrated Circuit Systems, Inc. ICS9LPRS511 Advance Information 1137—09/05/08 I2C Table: WD Safe Frequency Control Register Byte 10 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 SWD2 WD Soft Alarm Timer Bit 2 RW 1 Bit 6 SWD1 WD Soft Alarm Timer Bit 1 RW 1 Bit 5 SWD0 WD Soft Alarm Timer Bit 0 RW 1 Bit 4 WD SF4 RW 0 Bit 3 WD SF3 RW 0 Bit 2 WD SF2 RW 0 Bit 1 WD SF1 RW 0 Bit 0 WD SF0 RW 0 I 2C Table: CPU PLL Frequency Control Register Byte 11 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div1 N Divider Prog bit 1 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X I2C Table: CPU PLL Frequency Control Register (DOC0 = 0) Byte 12 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X I2C Table: CPU PLL Spread Spectrum Control Register Byte 13 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X Bit 4 SSP4 RW X Bit 3 SSP3 RW X Bit 2 SSP2 RW X Bit 1 SSP1 RW X Bit 0 SSP0 RW X I2C Table: CPU PLL Spread Spectrum Control Register Byte 14 Name Control Function Type PWD A/B/C/D/E/H/J Bit 7 SSP15 RW 0 Bit 6 SSP14 RW X Bit 5 SSP13 RW X Bit 4 SSP12 RW X Bit 3 SSP11 RW X Bit 2 SSP10 RW X Bit 1 SSP9 RW X Bit 0 SSP8 RW X 1 Spread Spectrum Programming bit(14:8) Watch Dog Safe Freq Programming bits 1 0 Writing to these bit will configure the safe frequency as Byte10 bit (4:0). 0 1 The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) 0 Spread Spectrum Programming bit(7:0) These Spread Spectrum bits in Byte 13 and 14 will program the spread percentage of CPU PLL M Divider Programming bit (5:0) N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) 1 1 These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. These Spread Spectrum bits in Byte 13 and 14 will program the spread percentage of CPU PLL 0 The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) 0 |
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