2

Integrated

Circuit

Systems, Inc.

ICS9LPRS511

Advance Information

1137—09/05/08

Pin Description

Pin#

Pin Name

Type Pin Description

1

**RLATCH

IN

Asynchronous input pin used in combination with VTTPWRGD signal to determine

whether to reset I2c.

2

GND

PWR Ground pin.

3

VDD

PWR Power supply, nominal 3.3V

4

**GSEL/24.576Mhz

I/O

Latch input to select PCIEX0 and DOT96 output. GSEL = 1, selects DOT 96Mhz ;

GSEL = 0, selects PCIEX0. /

24.576Mhz clock output

5

VDDPCI

PWR Power supply for PCI clocks, nominal 3.3V

6

GND

PWR Ground pin.

7

**DOC_1

IN

Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will

transition to a preprogrammed value in the I2c.

8

PCICLK0

OUT

PCI clock output.

9

PCICLK1_3x

OUT

Programmable 3x strength PCICLK, default 2x

10

FSLB/PCICLK2_2x

I/O

3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see

input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.

11

SELRSET/RESET#/PCICLK3

I/O

Latch select input pin. SELRSET = 0, selects PCICLK, SELRSET = 1 selects

RESET#

12

PCICLK4

OUT

PCI clock output.

13

**DOC_0

IN

Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will

transition to a preprogrammed value in the I2c.

14

VDD48

PWR Power pin for the 48MHz output.3.3V

15

FSLA/USB_48MHz

I/O

3.3V tolerant input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.

16

*SEL24_48#/24_48Mhz

I/O

Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 =

48MHz.

17

GND

PWR Ground pin.

18

Vtt_PwrGd/WOL_STOP#

IN

This active high 3.3V LVTTL input is a level sensitive strobe used to determine when

latch inputs are valid and are ready to be sampled / Asynchronous active low input pin

that stops all outputs except free running 25Mhz

19

DOT96T_LR/PCIeT_LR0

OUT

True clock of differential pair for 96.00MHz non-spreading DOT clock/ True clock of

PCIEX0 Clock pair - selectable by GSEL; both 0.75V differential pairs are 0.75V push-

pull outputs with integrated 33ohm series resistor.

20

DOT96C_LR/PCIeC_LR0

OUT

Complementary clock of differential pair for 96.00MHz non-spreading DOT clock/

Complementary clock of PCIEX0 Clock pair - selectable by GSEL; both 0.75V

differential pairs are 0.75V push-pull outputs with integrated 33ohm series resistor.

21

GND

PWR Ground pin.

22

PCIeT_LR1

OUT

True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm

series resistor

23

PCIeC_LR1

OUT

Complement clock of 0.75V differential push-pull PCI_Express pair with integrated

33ohm series resistor

24

PCIeT_LR2

OUT

True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm

series resistor

25

PCIeC_LR2

OUT

Complement clock of 0.75V differential push-pull PCI_Express pair with integrated

33ohm series resistor

26

GND

PWR Ground pin.

27

PCIeT_LR3

OUT

True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm

series resistor

28

PCIeC_LR3

OUT

Complement clock of 0.75V differential push-pull PCI_Express pair with integrated

33ohm series resistor

29

PCIeT_LR4

OUT

True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm

series resistor

30

PCIeC_LR4

OUT

Complement clock of 0.75V differential push-pull PCI_Express pair with integrated

33ohm series resistor

31

GND

PWR Ground pin.

32

VDDPCIEX

PWR Power supply for PCI Express clocks, nominal 3.3V