MPC8347 datasheet(19/108 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 18 provides the input AC timing specifications for the DDR SDRAM interface.

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 19 shows the DDR and DDR2 output AC timing specifications.

Table 18. DDR and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for

MDQS—MDQ/MECC/MDM

tCISKEW

400 MHz

–600

600

333 MHz

–750

750

266 MHz

–750

750

200 MHz

–750

750

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding

bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. This specification applies only to the DDR2 interface.

3. This specification applies only to the DDR interface.

Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)

tMCK

510

ADDR/CMD/MODT output setup with respect to MCK

tDDKHAS

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

ADDR/CMD/MODT output hold with respect to MCK

tDDKHAX

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

MCS(n) output setup with respect to MCK

tDDKHCS

400 MHz

1.95

—

333 MHz

2.40

—

266 MHz

3.15

—

200 MHz

4.20

—

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