MPC8347 datasheet(2/108 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

This section provides a high-level overview of the MPC8347EA features. Figure 1 shows the major

functional units within the MPC8347EA.

Figure 1. MPC8347EA Block Diagram

Major features of the MPC8347EA are as follows:

•

Embedded PowerPC e300 processor core; operates at up to 667 MHz

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the other Freescale processor families that implement the PowerPC

architecture

•

Double data rate, DDR1/DDR2 SDRAM memory controller

— Programmable timing supporting DDR1 and DDR2 SDRAM

— 32- or 64-bit data interface, up to 400 MHz data rate for TBGA, 266 MHz for PBGA

— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable

— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports

— Full error checking and correction (ECC) support

— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep-mode support for SDRAM self refresh

— Auto refresh

DUART

Dual I2C

Timers

GPIO

Security

Interrupt

Controller

Dual

Role

High-Speed

Local Bus

DDR

SDRAM

Controller

Host

32KB

D-Cache

e300 Core

32KB

I-Cache

USB 2.0

10/100/1000

SEQ

PCI

DMA

Ethernet

10/100/1000

Ethernet

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