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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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MB90F482 数据表(PDF) 64 Page - fujitsu semiconductor |
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MB90F482 数据表(HTML) 64 Page - fujitsu semiconductor |
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64 / 113 page  MB90480/485 Series 64 (2) Block Diagram SCM HCLK SCLK MCM WS1 WS0 SCS MCS CS1 CS0 STP SLP SPL RST TMD CG1 CG0 Re- served 2 2 X0A X1A RST X0 X1 MCLK PLL2 Low-power mode control register (LPMCR) Interrupt release CPU internal operation selec tor Pin high-impedance control circuit Clock selector Sub clock generator circuit pin Oscillator stabiliza- tion wait period selector Clock select register (CKSCR) Timebase timer pin Peripheral clock control circuit Internal reset generator circuit Standby control circuit PLL multiplier circuit pin pin To watchdog timer × 1024 HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock Standby control circuit CPU clock control circuit pin System clock generator circuit × 2 × 2 × 4 × 4 × 4 × 2 Clock generator module Machine clock Oscillator stabilization wait release Pin high-impedance control CPU clock Internal reset Stop, sleep signals Stop signal Peripheral clock Intermittent cycle selection × 4 PLL output select register (PLLOS) |
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