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MB90F482 数据表(PDF) 27 Page - fujitsu semiconductor |
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MB90F482 数据表(HTML) 27 Page - fujitsu semiconductor |
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27 / 113 page  MB90480/485 Series 27 (Continued) ×: Interrupt request flag not cleared by the interrupt clear signal. If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request flags at the DMAC interrupt clear signal. Therefore if either of the two sources uses the DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corresponding resource should be set to “0” and interrupt requests from that resource should be handled by software polling. * : Caution : The FLASH write/erase, timebase timer, and watch timer cannot be used at the same time. Interrupt source µµµµDMA channel number Interrupt vector Interrupt control register Number Address Number Address I2C interface (MB90485 series only) × #39 FFFF60H ICR14 0000BEH A/D conversion 15 #40 FFFF5CH FLASH write/erase, timebase timer,watch timer * × #41 FFFF58H ICR15 0000BFH Delay interrupt generator module × #42 FFFF54H |
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