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MB90F482 数据表(PDF) 33 Page - fujitsu semiconductor |
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MB90F482 数据表(HTML) 33 Page - fujitsu semiconductor |
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33 / 113 page  MB90480/485 Series 33 (2) Block Diagram MD1 MD0 CS2 CS1 CS0 SCKE SOE PEN P SBL CL A/D REC REX TXE PE ORE FRE RDRF TDRE BDS RIE TIE F2MC-16LX BUS SIDR SODR SOT0 SCK0 SIN0 Control signal PPG1 (internal connection) External clock Clock select circuit Receiving status decision circuit DMAC receiving error generation circuit (to CPU) Receiving control circuit Receiving control circuit Start bit detect circuit Receive bit counter Receiving parity counter Receiving shifter Receiving control circuit Sending clock Receiving interrupt (to CPU) Sending interrupt (to CPU) Sending control circuit Send start circuit Send bit counter Send parity counter Sending shifter Sending start SMR register Control signal SCR register SSR register Proprietary baud rate generator |
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