BLP5LA55SG

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© Ampleon Netherlands B.V. 2023. All rights reserved.

Product data sheet

Rev. 1 — 7 April 2023

3 of 20

BLP5LA55SG

Power LDMOS transistor

6.

Characteristics

7.

Test information

7.1 Ruggedness in class-AB operation

The BLP5LA55SG is capable of withstanding a load mismatch corresponding to

VSWR = 65 : 1 through all phases under the following conditions: VDS =13.6V;

IDq =100 mA; PL =55W (CW); f = 520MHz.

Table 6.

DC characteristics

Tj = 25 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V(BR)DSS drain-source breakdown voltage VGS =0V; ID =2.25mA

30

-

-

V

VGS(th)

gate-source threshold voltage

VDS = 10 V; ID = 225 mA

1.5

1.9

2.5

V

IDSS

drain leakage current

VGS =0V; VDS =32 V

-

-

1.4

A

IDSX

drain cut-off current

VGS =VGS(th) + 3.75 V;

VDS = 10 V

-38

-

A

IGSS

gate leakage current

VGS =11V; VDS = 0 V

-

-

140

nA

gfs

forward transconductance

VDS =10V; ID = 11.25 A

-

15

-

S

RDS(on)

drain-source on-state resistance

VGS =VGS(th) + 3.75 V;

ID =7.88 A

-60

-

m



Table 7.

AC characteristics

Tj =25 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min Typ

Max Unit

Ciss

input capacitance

VGS = 0 V; VDS = 13.6 V; f = 1 MHz

-

173.5 -

pF

Coss

output capacitance

VGS = 0 V; VDS = 13.6 V; f = 1 MHz

-

106.1 -

pF

Crss

reverse transfer

capacitance

VGS = 0 V; VDS =13.6V; f=1MHz

-

1.3

-

pF

Table 8.

RF characteristics

Test signal: CW at VDS =13.6 V; IDq =100 mA; Tcase = 25 C; unless otherwise specified; in a

class-AB production board measured at frequencies of 520 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Gp

power gain

PL = 55 W

18.0

19.6

-

dB

RLin

input return loss

PL =55 W

-

15.3

-

dB



D

drain efficiency

PL = 55 W

72.0

75.0

-

%