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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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T48C862-R3 数据表(PDF) 70 Page - ATMEL Corporation |
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T48C862-R3 数据表(HTML) 70 Page - ATMEL Corporation |
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70 / 107 page  70 T48C862-R3 4554A–4BMCU–02/03 Figure 66. Example of 8-bit Synchronous Transmit Operation Figure 67. Example of 8-bit Synchronous Receive Operation 9-bit Shift Mode (MCL) In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the MCL start and stop conditions are automatically generated whenever the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol, the output data is always changed in the clock low phase and shifted in on the high phase. 76543 21 0 7 6 543 210 7 6 54 321 0 msb lsb tx data 1 tx data 2 tx data 3 msb lsb msb lsb Write STB (tx data 2) Write STB (tx data 3) Write STB (tx data 1) SC SD SIR SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) ACT 43210 7 6 543 210 msb lsb rx data 1 rx data 2 rx data 3 msb lsb msb lsb Read SRB (rx data 2) Read SRB (rx data 3) Read SRB (rx data 1) SC SD SIR SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) ACT 7 6 5 4 3210 76 5 7 6 5 4 |
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