T48C862-R3 datasheet(92/107 Pages) ATMEL

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T48C862-R3

4554A–4BMCU–02/03

Control Byte Format

EEPROM

The EEPROM has a size of 2

´ 512 bits and is organized as 32 x 16-bit matrix each. To

read and write data to and from the EEPROM the serial interface must be used. The

interface supports one and two byte write accesses and one to n-byte read accesses to

the EEPROM.

EEPROM – Operating Modes

The operating modes of the EEPROM are defined via the control byte. The control byte

contains the row address, the mode control bits and the read/not-write bit that is used to

control the direction of the following transfer. A "0" defines a write access and a "1" a

read access. The five address bits select one of the 32 rows of the EEPROM memory to

be accessed. For all accesses the complete 16-bit word of the selected row is loaded

into a buffer. The buffer must be read or overwritten via the serial interface. The two

mode control bits C1 and C2 define in which order the accesses to the buffer are per-

formed: High byte – low byte or low byte – high byte. The EEPROM also supports

autoincrement and autodecrement read operations. After sending the start address with

the corresponding mode, consecutive memory cells can be read row by row without

transmission of the row addresses.

Two special control bytes enable the complete initialization of EEPROM with "0" or

with "1".

Write Operations

The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the

START condition followed by a write control byte and one or two data bytes from the

master. It is completed via the STOP condition from the master after the acknowledge

cycle.

The programming cycle consists of an erase cycle (write "zeros") and the write cycle

(write "ones"). Both cycles together take about 10 ms.

Acknowledge Polling

If the EEPROM is busy with an internal write cycle, all inputs are disabled and the

EEPROM will not acknowledge until the write cycle is finished. This can be used to

detect the end of the write cycle. The master must perform acknowledge polling by

sending a start condition followed by the control byte. If the device is still busy with the

write cycle, it will not return an acknowledge and the master has to generate a stop con-

dition or perform further acknowledge polling sequences. If the cycle is complete, it

returns an acknowledge and the master can proceed with the next read or write cycle.

Write One Data Byte

Write Two Data Bytes

Write Control Byte Only

EEPROM Address

Mode

Control Bits

Read/

NWrite

Start

A4A3A2A1A0

R/NW

Ackn

Start

Control byte

Ackn

Data byte

Ackn

Data byte

Ackn

Stop

Start

Control byte

Data byte 1

Stop

Start

Control byte

Data byte 1

Data byte 2

Stop

Start

Control byte

Stop

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