T48C862-R3 datasheet(73/107 Pages) ATMEL

73 / 107 page

T48C862-R3

4554A–4BMCU–02/03

MCL Bus Protocol

The MCL protocol constitutes a simple 2-wire bi-directional communication highway via

which devices can communicate control and data information. Although the MCL proto-

col can support multi-master bus configurations, the SSI in MCL mode is intended for

use purely as a master controller on a single master bus system. So all reference to

multiple bus control and bus contention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit.

Normally the communication channel is opened with a so-called start condition, which

initializes all devices connected to the bus. This is then followed by a data telegram,

transmitted by the master controller device. This telegram usually contains an 8-bit

address code to activate a single slave device connected onto the MCL bus. Each slave

receives this address and compares it with its own unique address. The addressed

slave device, if ready to receive data, will respond by pulling the SD line low during the

9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting

this affirmative acknowledge then opens a connection to the required slave. Data can

then be passed back and forth by the master controller, each 8-bit telegram being

acknowledged by the respective recipient. The communication is finally closed by the

master device and the slave device put back into standby by applying a stop condition

onto the bus.

Figure 70. MCL Bus Protocol 1

Bus not busy (1)

Both data and clock lines remain HIGH.

Start data transfer (2)

A HIGH to LOW transition of the SD line while the clock (SC)

is HIGH defines a START condition

Stop data transfer (3)

A LOW to HIGH transition of the SD line while the clock (SC)

is HIGH defines a STOP condition.

Data valid (4)

The state of the data line represents valid data when,

after START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Acknowledge

All address and data words are serially transmitted to and

from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to

acknowledge word receipt.

(2)

(1)

(4)

(3)

(1)

Start

condition

Data

valid

Data

change

Data

valid

Stop

condition

T48C862-R3 数据表(PDF) 73 Page - ATMEL Corporation

T48C862-R3 数据表(HTML) 73 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

T48C862-R3 数据表(PDF) 73 Page - ATMEL Corporation

T48C862-R3 数据表(HTML) 73 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载