ADV7392EBZ datasheet(58/96 Pages) AD

58 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 58 of 96

Coring Gain Border—Subaddress 0xA3, Bits[3:0]

These four bits are assigned to the gain factor applied to border

areas. In DNR mode, the range of gain values is 0 to 1 in

increments of 1/8. This factor is applied to the DNR filter

output that lies below the set threshold range. The result is then

subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

Coring Gain Data—Subaddress 0xA3, Bits[7:4]

These four bits are assigned to the gain factor applied to the luma

data inside the MPEG pixel block. In DNR mode, the range of

gain values is 0 to 1 in increments of 1/8. This factor is applied

to the DNR filter output that lies below the set threshold range.

The result is then subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output that lies above the threshold range. The result is added to

the original signal.

O XXXXXXO O XXXXXXO

DNR27 TO DNR24 = 0x01

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

APPLY BORDER

CORING GAIN

APPLY DATA

CORING GAIN

Figure 80. SD DNR Offset Control

DNR Threshold—Subaddress 0xA4, Bits[5:0]

These six bits are used to define the threshold value in the range

of 0 to 63. The range is an absolute value.

Border Area—Subaddress 0xA4, Bit 6

When this bit is set to Logic 1, the block transition area can be

defined to consist of four pixels. If this bit is set to Logic 0, the

border transition area consists of two pixels, where one pixel

refers to two clock cycles at 27 MHz.

720 × 485 PIXELS

(NTSC)

8 × 8 PIXEL BLOCK

2-PIXEL

BORDER DATA

8 × 8 PIXEL BLOCK

Figure 81. SD DNR Border Area

Block Size—Subaddress 0xA4, Bit 7

This bit is used to select the size of the data blocks to be

processed. Setting the block size control function to Logic 1

defines a 16 pixel × 16 pixel data block, and Logic 0 defines an

8 pixel × 8 pixel data block, where one pixel refers to two clock

cycles at 27 MHz.

DNR Input Select—Subaddress 0xA5, Bits[2:0]

These three bits are assigned to select the filter that is applied to

the incoming Y data. The signal that lies in the pass band of the

selected filter is the signal processed by DNR. Figure 82 shows

the filter responses selectable with this control.

FILTER C

FILTER B

FILTER A

FILTER D

FREQUENCY (MHz)

0.2

0.4

0.6

0.8

1.0

Figure 82. SD DNR Input Select

DNR Mode—Subaddress 0xA5, Bit 4

This bit controls the DNR mode selected. Logic 0 selects DNR

mode; Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high

frequency signals as probable noise and subtracting this noise

from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal

that lies below the set threshold, assumed to be noise, from the

original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a

fraction of the signal that lies above the set threshold to the

original signal because this data is assumed to be valid data and

not noise. The overall effect is that the signal is boosted (similar

to using the extended SSAF filter).

Block Offset Control—Subaddress 0xA5, Bits[7:4]

Four bits are assigned to this control that allows a shift in the

data block of 15 pixels maximum. The coring gain positions are

fixed. The block offset shifts the data in steps of one pixel such

that the border coring gain factors can be applied at the same

position regardless of variations in input timing of the data.

ADV7392EBZ 数据表(PDF) 58 Page - Analog Devices

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