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ADV7392EBZ 数据表(PDF) 91 Page - Analog Devices |
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ADV7392EBZ 数据表(HTML) 91 Page - Analog Devices |
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91 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 91 of 96 Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x1C 625p @ 50 Hz. EAV/SAV synchroniza- tion. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 97. 16-Bit 625p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x18 625p @ 50 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x1C 625p @ 50 Hz. EAV/SAV synchroniza- tion. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x1C 625p @ 50 Hz. EAV/SAV synchroniza- tion. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. |
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