ADV7393EBZ datasheet(63/96 Pages) AD

63 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 63 of 96

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–30

–60

–90

–120

–150

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–210

–240

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

GROUP DELAY (Seconds)

PHASE (Degrees)

MAGNITUDE (dB)

21n

18n

15n

12n

24n

Figure 89. Output Filter Plot for SD, 16× Oversampling

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–20

–30

–40

–50

–60

–70

–80

–90

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

GROUP DELAY (Seconds)

PHASE

(Degrees)

320

240

160

–80

–160

–240

480

400

14n

12n

10n

18n

16n

Figure 90. Output Filter Plot for ED, 8× Oversampling

–50

FREQUENCY (MHz)

CIRCUIT FREQUENCY RESPONSE

100

–10

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–40

200

–200

120

–40

–120

GROUP DELAY (Seconds)

PHASE

(Degrees)

MAGNITUDE (dB)

Figure 91. Output Filter Plot for HD, 4× Oversampling

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADV739x is a highly integrated circuit containing both

precision analog and high speed digital circuitry. It has been

designed to minimize interference effects on the integrity of the

analog circuitry by the high speed digital circuitry. It is imperative

that these same design and layout techniques be applied to the

system-level design so that optimal performance is achieved.

The layout should be optimized for lowest noise on the

ADV739x power and ground planes by shielding the digital

inputs and providing good power supply decoupling.

It is recommended to use a 4-layer printed circuit board with

ground and power planes separating the signal trace layer and

the solder side layer.

Component Placement

Component placement should be carefully considered to

separate noisy circuits, such as clock signals and high speed

digital circuitry from analog circuitry.

The external loop filter components and components connected

to the COMP and RSET pins should be placed as close as possible

to and on the same side of the PCB as the ADV739x. Adding

vias to the PCB to get the components closer to the ADV739x is

not recommended.

It is recommended that the ADV739x be placed as close as

possible to the output connector, with the DAC output traces as

short as possible.

The termination resistors on the DAC output traces should be

placed as close as possible to and on the same side of the PCB as

the ADV739x. The termination resistors should overlay the

PCB ground plane.

External filter and buffer components connected to the DAC

outputs should be placed as close as possible to the ADV739x to

minimize the possibility of noise pickup from neighboring

circuitry, and to minimize the effect of trace capacitance on

output bandwidth. This is particularly important when

operating in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω).

Power Supplies

It is recommended that a separate regulated supply be provided

for each power domain (VAA, VDD, VDD_IO, and PVDD). For

optimal performance, linear regulators rather than switch mode

regulators should be used. If switch mode regulators must be

used, care must be taken with regard to the quality of the output

voltage in terms of ripple and noise. This is particularly true for

the VAA and PVDD power domains. Each power supply should be

individually connected to the system power supply at a single

point through a suitable filtering device, such as a ferrite bead.

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