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ADV7393EBZ 数据表(PDF) 90 Page - Analog Devices |
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ADV7393EBZ 数据表(HTML) 90 Page - Analog Devices |
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90 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 90 of 96 ENHANCED DEFINITION Table 89. ED Configuration Scripts Input Format Input Data Width Synchronization Format Input Color Space Output Color Space Table Number 525p 8-Bit DDR EAV/SAV YCrCb YPrPb Table 98 525p 8-Bit DDR EAV/SAV YCrCb RGB Table 100 525p 10-Bit DDR EAV/SAV YCrCb YPrPb Table 99 525p 10-Bit DDR EAV/SAV YCrCb RGB Table 101 525p 16-Bit SDR EAV/SAV YCrCb YPrPb Table 90 525p 16-Bit SDR HSYNC/VSYNC YCrCb YPrPb Table 91 525p 16-Bit SDR EAV/SAV YCrCb RGB Table 92 525p 16-Bit SDR HSYNC/VSYNC YCrCb RGB Table 93 625p 8-Bit DDR EAV/SAV YCrCb YPrPb Table 102 625p 8-Bit DDR EAV/SAV YCrCb RGB Table 104 625p 10-Bit DDR EAV/SAV YCrCb YPrPb Table 103 625p 10-Bit DDR EAV/SAV YCrCb RGB Table 105 625p 16-Bit SDR EAV/SAV YCrCb YPrPb Table 94 625p 16-Bit SDR HSYNC/VSYNC YCrCb YPrPb Table 95 625p 16-Bit SDR EAV/SAV YCrCb RGB Table 96 625p 16-Bit SDR HSYNC/VSYNC YCrCb RGB Table 97 Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 91. 16-Bit 525p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x00 525p @ 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 92. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 93. 16-Bit 525p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x00 525p @ 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 94. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x1C 625p @ 50 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. Table 95. 16-Bit 625p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x18 625p @ 50 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. |
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