 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADV7393EBZ 数据表(PDF) 9 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADV7393EBZ 数据表(HTML) 9 Page - Analog Devices |
|
|
9 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 9 of 96 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 9. • t9 = Clock high time • t10 = Clock low time • t11 = Data setup time • t12 = Data hold time • t13 = Control output access time • t14 = Control output hold time In addition, refer to Table 30 for the ADV7390/ADV7391 input configuration and Table 31 for the ADV7392/ADV7393 input configuration. t9 CLKIN t10 CONTROL OUTPUTS HSYNC VSYNC Cr2 Cb2 Cr0 Cb0 IN MASTER/SLAVE MODE IN SLAVE MODE Y0 Y1 Y2 PIXEL PORT CONTROL INPUTS t12 t11 t13 t14 Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000) IN MASTER/SLAVE MODE IN SLAVE MODE CLKIN CONTROL OUTPUTS t9 t10 Cr2 Cb2 Cr0 Cb0 Y0 Y1 Y2 Y3 t12 t14 t11 t13 HSYNC VSYNC CONTROL INPUTS PIXEL PORT PIXEL PORT Figure 3. SD Input, 16-Bit 4:2:2 YCrCb (Input Mode 000) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
