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©2020 Renesas Electronics Corporation

January 7, 2020

ICS83940DI Datasheet

Function Tables

Table 3A. Clock Select Function Table

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.

Control Input

Clock

CLK_SEL

PCLK, nPCLK

LVCMOS_CLK

0

Selected

De-selected

1

De-selected

Selected

Inputs

Outputs

Input to Output Mode

Polarity

CLK_SEL

LVCMOS_CLK

PCLK

nPCLK

Q[0:17]

0–01

LOW

Differential to Single-Ended

Non-Inverting

0–10

HIGH

Differential to Single-Ended

Non-Inverting

0–0

Biased; NOTE

1

LOW

Single-Ended to Single-Ended

Non-Inverting

0–1

Biased; NOTE

1

HIGH

Single-Ended to Single-Ended

Non-Inverting

0–

Biased; NOTE

1

0

HIGH

Single-Ended to Single-Ended

Inverting

0–

Biased; NOTE

1

1

LOW

Single-Ended to Single-Ended

Inverting

10––

LOW

Single-Ended to Single-Ended

Non-Inverting

11––

HIGH

Single-Ended to Single-Ended

Non-Inverting