8

©2020 Renesas Electronics Corporation

January 7, 2020

ICS83940DI Datasheet

Table 5C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

NOTE: All parameters measured at 200MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output VDDO/2.

NOTE 2: Measured from VDD/2 to VDDO/2.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal

load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at VDDO/2.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

200

MHz

tPLH

Propagation

Delay

PCLK, nPCLK; NOTE 1, 5

ƒ

 150MHz

1.2

3.8

ns

LVCMOS_CLK; NOTE 2, 5

ƒ

 150MHz

1.5

3.2

ns

Propagation

Delay

PCLK, nPCLK; NOTE 1, 5

ƒ > 150MHz

1.5

3.7

ns

LVCMOS_CLK; NOTE 2, 5

ƒ > 150MHz

2.0

3.6

ns

t

sk(o)

Output Skew;

NOTE 3, 5

PCLK, nPCLK

Measured on the Rising

Edge

at VDDO/2

200

ps

LVCMOS_CLK

200

ps

t

sk(pp)

Part-to-Part Skew;

NOTE 6

PCLK, nPCLK

ƒ

 150MHz

2.6

ns

LVCMOS_CLK

ƒ

 150MHz

1.7

ns

Part-to-Part Skew;

NOTE 6

PCLK, nPCLK

ƒ > 150MHz

2.2

ns

LVCMOS_CLK

ƒ > 150MHz

1.7

ns

Part-to-Part Skew;

NOTE 4, 5

PCLK, nPCLK

Measured on the Rising

Edge

at VDDO/2

1.2

ns

LVCMOS_CLK

1.0

ns

tR / tF

Output Rise/Fall Time

0.5V to 1.8V

0.3

1.2

ns

odc

Output Duty Cycle

ƒ < 166MHz

40

60

%