DATA SHEET

ICS87004AG REVISION C DECEMBER 1, 2009

1

©2009 Integrated Device Technology, Inc.

1:4, Differential-to-LVCMOS/LVTTL

Zero Delay Clock Generator

ICS87004

General Description

The ICS87004 is a highly versatile 1:4 Differential-

to-LVCMOS/LVTTL Clock Generator and a member of

the HiPerClockS® family of High Performance Clock

Solutions from IDT. The ICS87004 has two selectable

clock inputs. The CLK0, nCLK0 and CLK1, nCLK1

pairs can accept most standard differential input levels. Internal bias

on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs

to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL

and can be configured as zero delay buffer, multiplier or divider and

has an input and output frequency range of 15.625MHz to 250MHz.

The reference divider, feedback divider and output divider are each

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the input

clock and the output clocks. The PLL_SEL pin can be used to

bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

Features

• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance

• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs

• CLKx/nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL

levels on CLK0 and CLK1 inputs

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration with

configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Fully integrated PLL

• Cycle-to-cycle jitter: 45ps (maximum)

• Output skew: 50ps (maximum)

• Static phase offset: 50ps ± 125ps (3.3V ± 5%), CLK0/nCLK0

• Full 3.3V or 2.5V output operating supply

• 5V tolerant inputs

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

HiPerClockS™

ICS

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

GND

Q0

VDDO

SEL0

SEL1

SEL2

SEL3

CLK_SEL

VDD

CLK0

nCLK0

GND

Q1

VDDO

GND

Q2

VDDO

Q3

MR

FB_IN

PLL_SEL

CLK1

nCLK1

VDDA

ICS87004

24-Lead TSSOP

7.8mm x 4.4mm x 0.925mm package body

G Package

Top View

Block Diagram

0

1

Q0

Q1

Q2

Q3

PLL_SEL

FB_IN

SEL0

SEL1

SEL2

SEL3

MR

CLK0

nCLK0

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

÷2, ÷4, ÷8, ÷16

÷32, ÷64, ÷128

Pullup/Pulldown

Pulldown

CLK_SEL Pulldown

Pulldown

Pulldown

CLK1

nCLK1 Pullup/Pulldown

Pulldown

Pullup

Pulldown

Pulldown

Pulldown

Pulldown

0

1

Pin Assignment