ICS87004AG REVISION C DECEMBER 1, 2009

2

©2009 Integrated Device Technology, Inc.

ICS87004 Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 12, 21

GND

Power

Power supply ground.

2, 20,

22, 24

Q0, Q3,

Q2, Q1

Output

Single-ended clock outputs. 7

Ω typical output impedance.

LVCMOS/LVTTL interface levels.

3, 19, 23

VDDO

Power

Output supply pins.

4, 5,

6, 7

SEL0, SEL1,

SEL2, SEL3

Input

Pulldown

Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

8

CLK_SEL

Input

Pulldown

Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW,

selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels.

9VDD

Power

Core supply pin.

10

CLK0

Input

Pulldown

Non-inverting differential clock input.

11

nCLK0

Input

Pullup/

Pulldown

Inverting differential clock input. VDD/2 default when left floating.

13

VDDA

Power

Analog supply pin.

14

nCLK1

Input

Pullup/

Pulldown

Inverting differential clock input. VDD/2 default when left floating.

15

CLK1

Input

Pulldown

Non-inverting differential clock input.

16

PLL_SEL

Input

Pullup

PLL select. Selects between the PLL and reference clock as the input to the

dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH,

selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.

17

FB_IN

Input

Pulldown

Feedback input to phase detector for regenerating clocks with “Zero Delay.”

Connect to one of the outputs. LVCMOS/LVTTL interface levels.

18

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the outputs to go low. When logic LOW, the internal dividers and the

outputs are enabled. LVCMOS / LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4pF

RPULLUP

Input Pullup Resistor

51

k

Ω

RPULLDOWN Input Pulldown Resistor

51

k

Ω

CPD

Power Dissipation

Capacitance (per output)

VDD, VDDO = 3.465V

23

pF

VDD, VDDO = 2.625V

17

pF

ROUT

Output Impedance

5

7

12

Ω